TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company's 2024 North America Technology Symposium. TSMC debuted the TSMC A16 technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

This year marks the 30th anniversary of TSMC's North America Technology Symposium, and more than 2,000 attended the event, growing from less than 100 attendees 30 years ago. The North America Technology Symposium in Santa Clara, California kicks off TSMC Technology Symposiums around the world in the coming months. The symposium also features an "Innovation Zone," designed to highlight the technology achievements of our emerging start-up customers.

IBM, at the 2023 IEEE International Electron Device Meeting (IEDM), demonstrated a concept nanosheet transistor that posts a near 100% performance improvement at the boiling point of nitrogen, of 77 Kelvin (-196 °C). Given how relatively industrialized and scaled out the manufacture, safe transport, storage, and use of liquid nitrogen is, this development potentially unlocks a new class of chips that attain top performance under liquid nitrogen cooling. Think a new generation of AI HPC accelerators that can instantly double their performance under LN2, provided a new kind of cooling solution is developed for data-centers.

Nanosheet transistors are the evolutionary next step to FinFETs, which have been driving semiconductor foundries since 16 nm, which could see their technical limits met at 3 nm. Nanosheets are expected to make their debut with 2 nm-class nodes such as the TSMC N2 and Intel 20A. At an operating temperature of 77 K, IBM's nanosheet device is claimed to offer a near doubling in performance, due to less charge carrier scattering, which results in lower power. Reducing scattering reduces resistance in the wires, letting electrons move through the device more quickly. Combined with lower power, devices can drive a higher current at a given voltage. Cooling also results in greater sensitivity between the device's on and off positions, so it takes lesser power to switch between the two states, resulting in lower power. This lower power means that transistor widths can be lowered, resulting in higher transistor densities, or smaller chips. As of now IBM is wrestling with a technical challenge concerning the transistor's threshold voltage, a voltage which is needed to create a conducting channel between the source and the drain.

During the European Technology Symposium 2023, TSMC presented additional details regarding the upcoming complementary FET (CFET) technology to power the next generation of silicon-based devices. With Nanosheet replacing FinFET, the CFET technology will do the same to the Gate All Around FET (GAAFET) Nanosheet nodes. As the company notes, CFET transistors are now in the TSMC labs and are being tested for performance, efficiency, and density. Compared to GAAFET, CFET will provide greater design in all of those areas, but it will require some additional manufacturing steps to get the chip working as intended. Integrating both p-type and n-type FETs into a single device, CFET will require the use of High NA EUV scanners with high precision and high power to manufacture it.

The use of CFET, as the roadmap shows, is one of the last steps in the world of silicon. It will require the integration of new materials into the manufacturing process, resulting in a greater investment into research and development that is in charge of node creation. Kevin Zhang, senior vice president at TSMC, responsible for technology roadmap and business development, notes: "Let me make a clarification on that roadmap, everything beyond the Nanosheet is something we will put on our [roadmap] to tell you there is still future out there. We will continue to work on different options. I also have the add on to the one-dimensional material-[based transistors] […], all of those are being researched on being investigated on the future potential candidates right now, we will not tell you exactly the transistor architecture will be beyond the Nanosheet."